# Reading pref.tcl
# //  Questa Intel Starter FPGA Edition-64
# //  Version 2021.2 win64 Apr 14 2021
# //
# //  Copyright 1991-2021 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //
# do uart_app_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Questa Intel Starter FPGA Edition-64 vmap 2021.2 Lib Mapping Utility 2021.04 Apr 14 2021
# vmap work rtl_work 
# Copying C:/intelFPGA_lite/21.1/questa_fse/win64/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart.v 
# -- Compiling module uart
# 
# Top level modules:
# 	uart
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx.v 
# -- Compiling module tx
# 
# Top level modules:
# 	tx
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_app.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_app.v 
# -- Compiling module uart_app
# 
# Top level modules:
# 	uart_app
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/user_app.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/user_app.v 
# -- Compiling module user_app
# 
# Top level modules:
# 	user_app
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_more_one.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_more_one.v 
# -- Compiling module rx_more_one
# 
# Top level modules:
# 	rx_more_one
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/baud_rate_en.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/baud_rate_en.v 
# -- Compiling module baud_rate_en
# 
# Top level modules:
# 	baud_rate_en
# End time: 12:40:11 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/scan_seg.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:11 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/scan_seg.v 
# -- Compiling module scan_seg
# 
# Top level modules:
# 	scan_seg
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_app.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_app.v 
# -- Compiling module rx_app
# 
# Top level modules:
# 	rx_app
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/seg_dev.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/seg_dev.v 
# -- Compiling module seg_dev
# 
# Top level modules:
# 	seg_dev
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx_app.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx_app.v 
# -- Compiling module tx_app
# 
# Top level modules:
# 	tx_app
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_engine.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_engine.v 
# -- Compiling module uart_engine
# 
# Top level modules:
# 	uart_engine
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_wrapper.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_wrapper.v 
# -- Compiling module uart_wrapper
# 
# Top level modules:
# 	uart_wrapper
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx_fifo.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/tx_fifo.v 
# -- Compiling module tx_fifo
# 
# Top level modules:
# 	tx_fifo
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_fifo.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/rx_fifo.v 
# -- Compiling module rx_fifo
# 
# Top level modules:
# 	rx_fifo
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_reg_if.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/uart_reg_if.v 
# -- Compiling module uart_reg_if
# 
# Top level modules:
# 	uart_reg_if
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/cpu_test_if.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/src/cpu_test_if.v 
# -- Compiling module cpu_test_if
# 
# Top level modules:
# 	cpu_test_if
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores/uart_pll.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores/uart_pll.v 
# -- Compiling module uart_pll
# 
# Top level modules:
# 	uart_pll
# End time: 12:40:12 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores/fifo.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:12 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/ip_cores/fifo.v 
# -- Compiling module fifo
# 
# Top level modules:
# 	fifo
# End time: 12:40:13 on Jun 20,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/db {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/db/uart_pll_altpll.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:13 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/db" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/db/uart_pll_altpll.v 
# -- Compiling module uart_pll_altpll
# 
# Top level modules:
# 	uart_pll_altpll
# End time: 12:40:13 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb {D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb/tb.v}
# Questa Intel Starter FPGA Edition-64 vlog 2021.2 Compiler 2021.04 Apr 14 2021
# Start time: 12:40:13 on Jun 20,2022
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb" D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb/tb.v 
# -- Compiling module tb
# 
# Top level modules:
# 	tb
# End time: 12:40:13 on Jun 20,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs="+acc"  tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclone10lp_ver -L rtl_work -L work -voptargs=""+acc"" tb 
# Start time: 12:40:13 on Jun 20,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 2 FSMs in module "rx_app(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "rx_more_one(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "tx(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "scan_seg(fast)".
# ** Warning: $MODEL_TECH/../intel/verilog/src/altera_mf.v(31791): (vopt-2685) [TFMPC] - Too few port connections for 'DCFIFO_MW'.  Expected 14, found 13.
# ** Warning: $MODEL_TECH/../intel/verilog/src/altera_mf.v(31791): (vopt-2718) [TFMPC] - Missing connection for port 'eccstatus'.
# ** Note: (vopt-143) Recognized 1 FSM in module "cpu_test_if(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "rx_fifo(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "tx_app(fast)".
# ** Note: (vopt-143) Recognized 1 FSM in module "tx_fifo(fast)".
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
# Loading work.tb(fast)
# Loading work.uart_app(fast)
# Loading work.uart_pll(fast)
# Loading altera_mf_ver.altpll(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast)
# Loading altera_mf_ver.MF_cycloneiii_pll(fast)
# Loading altera_mf_ver.cda_m_cntr(fast)
# Loading altera_mf_ver.cda_n_cntr(fast)
# Loading altera_mf_ver.cda_scale_cntr(fast)
# Loading altera_mf_ver.pll_iobuf(fast)
# Loading work.user_app(fast)
# Loading work.rx_app(fast)
# Loading work.tx_app(fast)
# Loading work.seg_dev(fast)
# Loading work.scan_seg(fast)
# Loading work.cpu_test_if(fast)
# Loading work.uart_reg_if(fast)
# Loading work.uart_wrapper(fast)
# Loading work.uart(fast)
# Loading work.baud_rate_en(fast)
# Loading work.tx(fast)
# Loading work.rx_more_one(fast)
# Loading work.uart_engine(fast)
# Loading work.rx_fifo(fast)
# Loading work.fifo(fast)
# Loading altera_mf_ver.dcfifo(fast)
# Loading altera_mf_ver.dcfifo_mixed_widths(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__1)
# Loading altera_mf_ver.dcfifo_async(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__2)
# Loading altera_mf_ver.dcfifo_dffpipe(fast)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__1)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__2)
# Loading altera_mf_ver.dcfifo_fefifo(fast)
# Loading altera_mf_ver.dcfifo_fefifo(fast__1)
# Loading altera_mf_ver.dcfifo_low_latency(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__3)
# Loading altera_mf_ver.ALTERA_MF_HINT_EVALUATION(fast)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__3)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__4)
# Loading work.tx_fifo(fast)
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
add wave -position insertpoint sim:/tb/uart_app_inst/user_app_inst/rx_app_inst/*
restart
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Note: (vsim-8009) Loading existing optimized design _opt
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=2.
# Loading work.tb(fast)
# Loading work.uart_app(fast)
# Loading work.uart_pll(fast)
# Loading altera_mf_ver.altpll(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast)
# Loading altera_mf_ver.MF_cycloneiii_pll(fast)
# Loading altera_mf_ver.cda_m_cntr(fast)
# Loading altera_mf_ver.cda_n_cntr(fast)
# Loading altera_mf_ver.cda_scale_cntr(fast)
# Loading altera_mf_ver.pll_iobuf(fast)
# Loading work.user_app(fast)
# Loading work.rx_app(fast)
# Loading work.tx_app(fast)
# Loading work.seg_dev(fast)
# Loading work.scan_seg(fast)
# Loading work.cpu_test_if(fast)
# Loading work.uart_reg_if(fast)
# Loading work.uart_wrapper(fast)
# Loading work.uart(fast)
# Loading work.baud_rate_en(fast)
# Loading work.tx(fast)
# Loading work.rx_more_one(fast)
# Loading work.uart_engine(fast)
# Loading work.rx_fifo(fast)
# Loading work.fifo(fast)
# Loading altera_mf_ver.dcfifo(fast)
# Loading altera_mf_ver.dcfifo_mixed_widths(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__1)
# Loading altera_mf_ver.dcfifo_async(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__2)
# Loading altera_mf_ver.dcfifo_dffpipe(fast)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__1)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__2)
# Loading altera_mf_ver.dcfifo_fefifo(fast)
# Loading altera_mf_ver.dcfifo_fefifo(fast__1)
# Loading altera_mf_ver.dcfifo_low_latency(fast)
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES(fast__3)
# Loading altera_mf_ver.ALTERA_MF_HINT_EVALUATION(fast)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__3)
# Loading altera_mf_ver.dcfifo_dffpipe(fast__4)
# Loading work.tx_fifo(fast)
run -all
#  Note : Cyclone 10 LP PLL locked to incoming clock
# Time: 80000  Instance: tb.uart_app_inst.uart_pll_inst.altpll_component.cycloneiii_pll.pll3
# ** Note: $stop    : D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb/tb.v(25)
#    Time: 3300 us  Iteration: 0  Instance: /tb
# Break in Module tb at D:/class/uart_txrx/uart_summary/uart/uart_fifo_checksum_cputest/uart_app/../tb/tb.v line 25
# End time: 14:02:48 on Jun 20,2022, Elapsed time: 1:22:35
# Errors: 0, Warnings: 2
